As memory devices, such as dynamic random access memories (DRAM), increase in density, it becomes statistically more likely that one or more short circuits will exist, such as between a cell plate and a word, i.e., row, line, a bit, i.e., column, line, or another portion of a memory device. For example, for a 4-megabit DRAM, the probability of having at least one such short circuit ranges between approximately 10%-20%, depending upon the particular manufacturing process used. Causes of such short circuits include particle contamination and process variability. Even memory devices manufactured in the cleanest fabrication facilities and by the most carefully controlled processes are not immune from such yield-reducing short circuits.
FIG. 1 is a schematic block diagram of a memory-cell array 10 of a memory device 12. The array 10 includes a number of substantially identical memory cells 13, which each include an access switch 14 and a storage device 16. As shown here, the access switch is a transistor 14, and the storage device is a capacitor 16. The memory cells 13 are arranged in rows 0-x and columns 0-n; one memory cell 13 is positioned at the intersection of each row and column. As shown, each row includes one row line ROW, and each column includes a pair of complementary column lines COL and COL. Thus, each memory cell 13 has a control terminal coupled to an associated row line and a data terminal coupled to an associated column line. Each pair of complementary column lines is coupled to a sense amplifier 18, which reads the data stored in an addressed memory cell 13 that is coupled to either of the pair of complementary column lines. The array 10 also includes equilibrate switches 20, each of which is coupled between a different pair of complementary column lines and has a control terminal coupled to an equilibrate line EQ. As shown here, the equilibrate switches are the transistors 20.
Additionally, the memory-cell array 10 includes a cell plate CP, which is typically a plane formed in a conductive layer of the memory device 12 in the vicinity of the array 10 as indicated by the dashed outline. Each memory cell 13 has a reference terminal that is coupled to the cell plate CP. More specifically, as shown, each capacitor 16 has a first plate 22, which is coupled to the associated access transistor 14, and a second plate 24, which is coupled to the cell plate CP. A voltage generator 26 generates from a supply voltage Vcc a reference or bias voltage, which is typically equal or approximately equal to Vcc/2. Typically, Vcc is approximately 5 volts, although in newer memory devices Vcc may be as low as 3.3 volts. The voltage generator 26 drives the cell plate CP with this bias voltage, which, as discussed below, reduces the stresses to which the capacitors 16 are subjected.
Each of the memory cells 13 stores a single bit of data. A voltage of approximately Vcc at the plate 22 indicates a positive voltage (i.e., the plate 22 is more positive than the plate 24) of Vcc/2 across the capacitor 16. This positive voltage corresponds to a first binary data value, typically a 1. Conversely, a voltage of approximately 0 at the plate 22 indicates a negative voltage of -Vcc/2 across the capacitor 16. This negative voltage corresponds to a second binary data value, typically a 0. Thus, a capacitor 16 of a memory cell 13 never has more than .vertline.Vcc/2.vertline. across it. The reduction in the voltage stresses (as compared with capacitors of prior memory devices that could have voltages of Vcc across them) that are applied to the capacitors 16 greatly increases their operational lifetime.
In operation of the memory device 12, before the cells 13 are read from or written to, control circuitry (not shown in FIG. 1) generates an equilibration signal on the line EQ to equilibrate via the transistors 20 each of the complementary pairs of column lines COL and COL. That is, the transistor 20 is closed to couple together COL and COL of each pair of column lines and to bring COL and COL to the same voltage level of approximately Vcc/2. (Typically, before the equilibration interval, one of the lines COL and COL of each pair is at a logic 0 or 0 volts, and the other is at a logic 1 or Vcc. By shorting the two lines together, the voltage on the first line rises from 0 to Vcc/2, and the voltage on the second line falls from Vcc to Vcc/2.) During the equilibration interval, the control circuitry drives the row lines ROW.sub.0 -ROW.sub.x with a voltage substantially equal to 0 volts to deactivate the memory cells 13.
After the equilibration interval, during a read cycle, the control circuitry drives the row line of the addressed memory cell 13 with a voltage approximately equal to Vcc to activate the addressed cell 13. The voltage on the plate 22 of the capacitor 16 is transferred via the transistor 14 to the complementary column line coupled to the addressed cell 13. The associated sense amplifier 18 compares this voltage level to the Vcc/2 on the other complimentary column line, drives the higher column line to Vcc and the lower column line to 0, and provides the data contents of the addressed cell 13 to read/write circuitry (not shown in FIG. 1).
After the equilibration interval, during a write cycle, the control circuitry drives the row line that is coupled to the addressed cell 13 with Vcc, and the read/write circuit drives the column line that is coupled to the addressed cell 13 with a voltage, either Vcc or 0, that corresponds to the value of the data bit to be stored in the addressed cell 13.
A problem may arise when either a row line, a column line, or another line becomes short-circuited to the cell plate CP. For example, if the line to which the cell plate CP is shorted is driven to 0 volts, the cell plate CP will gradually discharge to a voltage lower than Vcc/2. This discharging typically occurs because the voltage generator 20 cannot output enough current to compensate for the current lost via the short circuit. Likewise, if the line to which the cell plate CP is shorted is driven to Vcc, the cell plate CP will gradually charge to a voltage greater than Vcc/2. Either scenario may cause data storage errors, and worse, may generate voltages larger than Vcc/2 across, and thus may destroy, one or more of the capacitors 16. Because there is often no way to repair such a short circuit, the memory device 12 is often irreparably damaged, and must be discarded.
FIG. 2 is a cross-section of the array 10 of FIG. 1 that illustrates in more detail how a short circuit between the cell plate CP and a column line or a row line may occur. As shown, the array 10 includes a column line 24 that is electrically isolated from the cell plate CP by an insulating layer 26. A memory cell 13 includes a transistor 14 that has its source S coupled to the plate 28 of the capacitor 16. The other plate 24 is formed by the cell plate CP. Thus, the cell plate CP in effect forms a common plate for all the capacitors 16. An insulating layer 30 isolates the cell plate CP from the memory cell 13. A conductive via 32, which extends through the cell plate CP and the layers 26 and 30, couples the column line 24 to the drain D of the transistor 14. An insulating layer 34 surrounds the via 32, and thus isolates the via 32 from the cell plate CP. A row line 36, which is coupled to the memory cell 13, also acts as the gate G of the transistor 14.
As shown, if the insulator 34 is defective in the vicinity of the cell plate CP, the via 32 may contact the cell plate CP and thus cause a short circuit between the column line 24 and the cell plate CP. Furthermore, although not shown, a defect in the insulating layer 30 may cause a short circuit between the row line 36 and the cell plate CP. As stated above, even just one such short circuit may render the memory device 12 irreparably damaged.